1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Background Art
In recent years, attention has been drawn to a stress application technology called eSiGe (embedded SiGe) technology. In accordance with the eSiGe technology, peripheral regions of a pMOSFET are recessed to embed SiGe films in the regions by selective epitaxial growth to thereby apply stress to a channel region of the pMOSFET. This causes strain within the channel region of the pMOSFET so that the mobility in the channel region of the pMOSFET is improved. As a similar technology, there also exists a technology to recess peripheral regions of an nMOSFET to embed SiC films in the regions by selective epitaxial growth to thereby apply stress to a channel region of the nMOSFET. This causes strain within the channel region of the nMOSFET so that the mobility in the channel region of the nMOSFET is improved. However, in these stress application technologies, there are problems as described below.
As an embedding technology of the SiGe films, a technology called Σ-shape technology is known (see: IDEM2005, “High Performance 30 nm Gate Bulk CMOS for 45 nm Node with Σ-shaped SiGe-SD”, H. Ohta et al.). In accordance with the Σ-shape technology, the peripheral regions are recessed by isotropic etching to thereby protrude the embedded regions of the SiGe films in a direction of the channel region. Thereby, the width of a substrate under the pMOS is narrowed, so that the stress applied to the channel region is increased. In the Σ-shape technology, by increasing an amount of protrusion of the embedded regions of the SiGe films, it is possible to increase the stress. However, in the case where the stress is increased by such a method, the fact that the width of the substrate under the PMOS is required to be larger than zero results in the upper limit of the amount of protrusion, and results in the upper limit of the stress. In other words, employment of such a method of increasing the stress leads to limit. On the other hand, the stress can be increased also by increasing Ge concentration. However, there is a possibility that the increased Ge concentration may induce crystal defects, and may be a cause to lower the yield of an integrated circuit. Accordingly, it is desirable to avoid using a method of increasing Ge concentration as far as possible. It is to be noted that the Σ-shape technology can be applied also to embedding of the SiC films.
In Japanese Patent No. 3651802, there is disclosed a method of processing the surface of a channel region by oxidizing it using plasma oxygen. In addition, a stress application technology using such a method is disclosed in ‘2007 Symposium on VLSI Technology Digest of Technical Papers, p. 46-47 “Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process”, J. Wang et al.’